14. Coprocessor 0
Format: CACHE op, offset(base)
The 16 bit offset is sign-extended and added to the contents of general register base to form a CacheOp virtual address (VA). The VA is translated to a physical address (PA) through the TLB, and the 5-bit opcode (decoded inTable 14-27) specifies a cache operation for that address, together with the affected cache. Operation of this instruction on any combination not listed in the tables below is undefined. The operation of this instruction on uncached addresses is also undefined.
More detailed descriptions of the CacheOps listed below are given separately, in Chapter 10, CACHE Instructions.
Table 14-27 CACHE Instruction Op Field Encoding 
Fill, Create Dirty, Hit WriteBack and Hit Set Virtual are not supported in the R10000 processor.
The R10000 processor adds two new CacheOps: Index Load Data (1102) and Index Store Data (1112). These changes are also reflected in the CP0 TagHi, TagLo and ECC registers.
The primary instruction and data caches have a block size of 16 words and 32 bytes (8 data words), respectively.
NOTE: A 32-bit instruction is predecoded into a 36-bit instruction word before entering the primary instruction cache. The instruction fetch addresses remain the same and are not affected by the predecode.
The secondary cache, a unified cache, has a block size of either 64 or 128 bytes, configurated during reset. For a cache of 2CACHESIZE bytes with 2BLOCKSIZE bytes per tag,
VACACHESIZE-2..BLOCKSIZE
specifies the block for the primary cache, and
PACACHESIZE-2..BLOCKSIZE
specifies the block for the secondary cache.
For the Index CacheOps, address bit 0 is used to specify the way, 0 or 1, for the CacheOp. For this reason, bit 0 is not checked for alignment-type Address Error exception for the Index CacheOps. For CacheOps that access data in caches,
VABLOCKSIZE-1..2
specifies a word within a block for primary caches, and
PABLOCKSIZE-1..3
specifies a doubleword in the secondary cache.
A cache hit accesses the specified cache as normal data references, and performs the specified operation if the cache block contains valid data at the specified physical address. If the cache line is invalid or contains a differing physical address (a cache miss), no operation is performed. Since the R10000 processor uses 2-way set associative caches, the Hit operation performs tag comparison in both ways of the cache. No index needs to be provided for such CacheOps. If both ways register a hit, the execution of the CacheOp is undefined.
Write back from the primary data cache goes to the secondary cache, and write back from the secondary cache goes to the system interface. The primary data cache is written back to the secondary cache before the secondary cache is written back to the system interface; the address to be written is based by the cache tag, rather than the translated PA from the CacheOp instruction. A secondary cache write back also interrogates the primary data cache for any dirty inconsistent data.
When a line is invalidated in the secondary cache, all subset lines in the primary caches are also invalidated.
CacheOps are serialized with respect to cached loads/stores and CP0 instructions. Therefore, in general, there are no hazards for CacheOps. However, if the CacheOps modify the current instruction fetching stream, they may not work properly since the instruction fetch pipeline usually prefetches and buffers instructions and CacheOps are not serialized with respect to the instruction fetch pipeline. Programmers should be aware of such potential hazards; one solution is to put a COP0 instruction after the CacheOp to prevent the speculative execution and force the CacheOp to complete, and then use a Jump Register instruction to flush the instruction fetch pipeline. Succeeding instructions will then be re-fetched from caches.
If CP0 is not usable, a Coprocessor Unusable exception is taken. CacheOps may induce Address Error or TLBL exceptions (Refill or Invalid) during address translation, but never take a TLBS or Mod exception. The virtual address is used to index the cache for an Index CacheOp, but need not match the cache physical tag; unmapped addresses may be used to avoid TLB exceptions.
The R10000 processor does not support the CE bit, and programmers must supply correct parity bits or ECC for some CacheOps.
The R10000 processor supports the CH bit for secondary CacheOps, Hit Invalidate, and Hit WriteBack Invalidate. As in the R4400, a hit sets the CH bit of the Status register, and a miss resets it. This bit is readable and writable by software.
For a detailed description of the individual CacheOps, see Chapter 10, CACHE Instructions.
Operation: 
Exceptions:
Coprocessor unusable exception
